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Instructions that refer to 64-bit registers are automatically performed with 64-bit precision. The addressing modes in 64-bit mode are similar but not identical to x86. The next three parameters are passed in remaining registers, while the rest are passed on the stack. The this pointer is passed as an implicit first parameter. The calling convention for C++ is similar. Rbx, rbp, rdi, rsi, r12- r15 are nonvolatile.

The called function can use this space to spill the contents of registers to the stack.Īny additional arguments are passed on the stack.Īn integer or pointer return value is returned in the rax register, while a floating-point return value is returned in xmm0. The caller reserves space on the stack for arguments passed in registers. The first four floating-point parameters are passed in the first four SSE registers, xmm0- xmm3. The first four integer or pointer parameters are passed in the rcx, rdx, r8, and r9 registers.

This calling convention takes advantage of the increased number of registers available on 圆4: Unlike the x86, the C/C++ compiler only supports one calling convention on 圆4.

The original set of eight 128-bit SSE registers is increased to sixteen. (These registers overlap with the x87 registers.) The 圆4 processor also provides several sets of floating-point registers:Įight 64-bit MMX registers. The instruction pointer eip and flags register have been extended to 64 bits ( rip and rflags, respectively). The high 8 bits of ax, bx, cx, and dx are still addressable as ah, bh, ch, dh but can't be used with all types of operands. Operations that output to 8-bit or 16-bit subregisters aren't zero-extended (this is compatible x86 behavior). Operations that output to a 32-bit subregister are automatically zero-extended to the entire 64-bit register. The following table specifies the assembly-language names for the lower portions of 64-bit registers. This includes registers, like esi, whose lower 8 bits weren't previously addressable. The lower 32 bits, 16 bits, and 8 bits of each register are directly addressable in operands. The new registers are named r8 through r15. For example, the 64-bit extension of eax is called rax. The 64-bit registers have names beginning with "r". X64 extends x86's 8 general-purpose registers to be 64-bit, and adds 8 new 64-bit registers. The instruction sets are almost identical. The term "圆4" includes both AMD 64 and Intel64. It provides a new 64-bit mode and a legacy 32-bit mode, which is identical to x86. The 圆4 architecture is a backwards-compatible extension of x86.